By Professor Sri Parameswaran

Conference Papers

Parameswaran S, 2001, 'Code placement in hardware software Co synthesis to improve performance and reduce cost', in Proceedings Design Automation and Test in Europe Date, pp. 626 - 632, http://dx.doi.org/10.1109/DATE.2001.915089

Rae A; Parameswaran S, 2000, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 147 - 152, http://dx.doi.org/10.1145/368434.368594

Boros VE; Rakic AD; Parameswaran S, 2000, 'High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system', in Proceedings Design Automation Conference, pp. 221 - 226, http://dx.doi.org/10.1145/337292.337395

Rae A; Parameswaran S, 1998, 'Application-specific heterogeneous multiprocessor synthesis using differential-evolution', in Proceedings of the International Symposium on System Synthesis, pp. 83 - 88, http://dx.doi.org/10.1109/isss.1998.730602

Parameswaran S; Guo H, 1997, 'Partitioning of system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 233 - 238

Parameswaran S; Guo H, 1997, 'Power reduction in pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 239 - 244

Guo H; Parameswaran S, 1997, 'Unfolding loops with interdetermine count in system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 82 - 87

Parameswaran S; Guo H, 1997, 'Power consumption in CMOS combinational logic blocks at high frequencies', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 195 - 200

Jha P; Parameswaran S; Dutt N, 1995, 'Reclocking for high level synthesis', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 49 - 54

Parkinson MF; Parameswaran S, 1995, 'Profiling in the ASP codesign environment', in Proceedings of the International Symposium on System Synthesis, pp. 128 - 133, http://dx.doi.org/10.1145/224486.224531

Kia SM; Parameswaran S, 1994, 'Design automation of self checking circuits', in European Design Automation Conference Proceedings, pp. 252 - 257

Kia SM; Parameswaran S, 1994, 'Novel architectures for TSC/CD and SFS/SCD synchronous controllers', in Proceedings of the IEEE VLSI Test Symposium, pp. 138 - 143

Parkinson MF; Taylor PM; Parameswaran S, 1994, 'C to VHDL converter in a codesign environment', in Spring 1994 Conference Proceedings VHDL International Users Forum VIUF 1994, pp. 100 - 109, http://dx.doi.org/10.1109/VIUF.1994.323960

Cheung N; Parameswarant S; Henkel J, 'Battery aware instruction generation for embedded processors', in Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., IEEE, pp. 553 - 556, presented at ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005, http://dx.doi.org/10.1109/aspdac.2005.1466225

Parkinson MF; Parameswaran S, 'Profiling in the ASP codesign environment', in Proceedings of the Eighth International Symposium on System Synthesis, IEEE Comput. Soc. Press, pp. 128 - 133, presented at Eighth International Symposium on System Synthesis, http://dx.doi.org/10.1109/isss.1995.520624

Rae A; Parameswaran S, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', in Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), IEEE, pp. 147 - 152, presented at ASP-DAC2000: Asia and South Pacific Design Automation Conference 2000, http://dx.doi.org/10.1109/aspdac.2000.835086

Conference Posters

Shwe S; Batra K; Yachide Y; Peddersen JM; Parameswaran S, 2015, 'RAPITIMATE: Rapid Performance Estimation of Pipelined Processing Systems Containing Shared Memory', presented at Design Automation Conference (DAC), 07 June 2015 - 11 June 2015

Ambrose JA; Peddersen JM; Yachide Y; Batra K; Parameswaran S, 2015, 'Sequential C-code to Distributed Pipelined Heterogeneous MPSoC Synthesis for Streaming Applications', New York, NY, pp. 216 - 223, presented at Design Automation Conference (DAC), New York, NY, 07 June 2015 - 11 June 2015

Theses / Dissertations

Parameswaran S, 1991, SPOT : A computer aided digital design system, http://dx.doi.org/10.14264/uql.2015.616

Preprints

Samarakoon H; Liyanage K; Ferguson J; Parameswaran S; Gamaarachchi H; Deveson I, 2024, Interactive visualisation of raw nanopore signal data with Squigualiser, http://dx.doi.org/10.1101/2024.02.19.581111

Samarakoon H; Wan YK; Parameswaran S; Göke J; Gamaarachchi H; Deveson I, 2024, Leveraging Basecaller’s Move Table to Generate a Lightweight k-mer Model, http://dx.doi.org/10.1101/2024.06.30.601452

Liyanage K; Samarakoon H; Parameswaran S; Gamaarachchi H, 2023, minimap2-fpga: Integrating hardware-accelerated chaining for efficient end-to-end long-read sequence mapping, http://dx.doi.org/10.1101/2023.05.30.542681

Shih PJ; Saadat H; Parameswaran S; Gamaarachchi H, 2022, Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices, http://arxiv.org/abs/2211.07340v1

Gong J; Saadat H; Gamaarachchi H; Javaid H; Hu XS; Parameswaran S, 2022, ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference, http://dx.doi.org/10.48550/arxiv.2209.04161

Li T; Parameswaran S, 2022, Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks, http://dx.doi.org/10.48550/arxiv.2204.05508

Samarakoon H; Ferguson J; Jenner S; Amos T; Parameswaran S; Gamaarachchi H; Deveson I, 2022, Flexible and efficient handling of nanopore sequencing signal data with slow5tools, http://dx.doi.org/10.1101/2022.06.19.496732

Li T; Hopkins B; Parameswaran S, 2020, SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation, http://arxiv.org/abs/2011.10249v2

Bayat A; Gamaarachchi H; Deshpande N; Wilkins M; Parameswaran S, 2020, Methods for De-novo Genome Assembly, http://dx.doi.org/10.20944/preprints202006.0324.v1

Ragel RG; Ambrose JA; Parameswaran S, 2015, SecureD: A Secure Dual Core Embedded Processor, http://dx.doi.org/10.48550/arxiv.1511.01946

Haque MS; Peddersen J; Parameswaran S, 2015, CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique, http://dx.doi.org/10.1109/ICCAD.2011.6105316

Haque MS; Peddersen J; Janapsatya A; Parameswaran S, 2015, DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy, http://dx.doi.org/10.1109/DATE.2010.5457153

Shah SM; Parameswaran S; Sharma V, 2014, Previous Messages Provide the Key to Achieve Shannon Capacity in a Wiretap Channel, http://dx.doi.org/10.1109/ICCW.2013.6649323

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