By Professor Sri Parameswaran

Preprints

Samarakoon H; Liyanage K; Ferguson J; Parameswaran S; Gamaarachchi H; Deveson I, 2024, Interactive visualisation of raw nanopore signal data with Squigualiser, http://dx.doi.org/10.1101/2024.02.19.581111

Samarakoon H; Wan YK; Parameswaran S; Göke J; Gamaarachchi H; Deveson I, 2024, Leveraging Basecaller’s Move Table to Generate a Lightweight k-mer Model, http://dx.doi.org/10.1101/2024.06.30.601452

Liyanage K; Samarakoon H; Parameswaran S; Gamaarachchi H, 2023, minimap2-fpga: Integrating hardware-accelerated chaining for efficient end-to-end long-read sequence mapping, http://dx.doi.org/10.1101/2023.05.30.542681

Shih PJ; Saadat H; Parameswaran S; Gamaarachchi H, 2022, Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices, http://arxiv.org/abs/2211.07340v1

Gong J; Saadat H; Gamaarachchi H; Javaid H; Hu XS; Parameswaran S, 2022, ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference, http://dx.doi.org/10.48550/arxiv.2209.04161

Li T; Parameswaran S, 2022, Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks, http://dx.doi.org/10.48550/arxiv.2204.05508

Samarakoon H; Ferguson J; Jenner S; Amos T; Parameswaran S; Gamaarachchi H; Deveson I, 2022, Flexible and efficient handling of nanopore sequencing signal data with slow5tools, http://dx.doi.org/10.1101/2022.06.19.496732

Gamaarachchi H; Samarakoon H; Jenner S; Ferguson J; Amos T; Hammond J; Saadat H; Smith M; Parameswaran S; Deveson I, 2021, SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis, http://dx.doi.org/10.1101/2021.06.29.450255

Li T; Hopkins B; Parameswaran S, 2020, SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation, http://arxiv.org/abs/2011.10249v2

Bayat A; Gamaarachchi H; Deshpande N; Wilkins M; Parameswaran S, 2020, Methods for De-novo Genome Assembly, http://dx.doi.org/10.20944/preprints202006.0324.v1

Gamaarachchi H; Lam CW; Jayatilaka G; Samarakoon H; Simpson J; Smith M; Parameswaran S, 2019, GPU Accelerated Adaptive Banded Event Alignment for Rapid Comparative Nanopore Signal Analysis, http://dx.doi.org/10.1101/756122

Gamaarachchi H; Parameswaran S; Smith M, 2018, Featherweight long read alignment using partitioned reference indexes, http://dx.doi.org/10.1101/386847

Ragel RG; Ambrose JA; Parameswaran S, 2015, SecureD: A Secure Dual Core Embedded Processor, http://arxiv.org/abs/1511.01946v1

Haque MS; Peddersen J; Parameswaran S, 2015, CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique, http://dx.doi.org/10.1109/ICCAD.2011.6105316

Haque MS; Peddersen J; Janapsatya A; Parameswaran S, 2015, DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy, http://dx.doi.org/10.1109/DATE.2010.5457153

Shah SM; Parameswaran S; Sharma V, 2014, Previous Messages Provide the Key to Achieve Shannon Capacity in a Wiretap Channel, http://dx.doi.org/10.1109/ICCW.2013.6649323

Back to profile page