By Professor Sri Parameswaran

Journal articles

Parameswaran S, 2016, 'Editorial Introduction of New Editor-in-Chief and Associate Editors', IEEE Embedded Systems Letters, 8, pp. 1, http://dx.doi.org/10.1109/LES.2016.2532418

Nawinne I; Javaid H; Ragel R; Radhakrishnan S; Parameswaran S, 2015, 'Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 34, pp. 1991 - 2003, http://dx.doi.org/10.1109/TCAD.2015.2445736

Ragel RG; Ambrose JA; Parameswaran S, 2015, 'SecureD: A Secure Dual Core Embedded Processor', , http://arxiv.org/abs/1511.01946v1

Javaid H; Shafique M; Henkel J; Parameswaran S, 2014, 'Energy-efficient adaptive pipelined MPSoCs for multimedia applications', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 33, pp. 663 - 676, http://dx.doi.org/10.1109/TCAD.2014.2298196

Javaid H; Ignjatovic A; Parameswaran S, 2014, 'Performance estimation of pipelined multiprocessor system-on-chips (MPSoCs)', IEEE Transactions on Parallel and Distributed Systems, 25, pp. 2159 - 2168, http://dx.doi.org/10.1109/TPDS.2013.268

Ambrose JA; Aldon N; Ignjatovic A; Parameswaran S, 2012, 'Differential Power Analysis in AES: A Crypto Anatomy', IJEI: International Journal of Engineering and Industries, 2, pp. 118 - 130, http://www.aicit.org/ijei/global/paper_detail.html?jname=IJEI&q=46

Ambrose JA; Ragel RG; Parameswaran S, 2012, 'Randomized Instruction Injection to Counter Power Analysis Attacks', ACM Transactions on Embedded Computing Systems (TECS), 11, pp. 28, http://dl.acm.org/citation.cfm?id=2345782

Ragel RG; Parameswaran S, 2011, 'A hybrid hardware-software technique to improve reliability in embedded processors', ACM Transactions on Embedded Computing Systems (TECS), 10, pp. Article number: 36, http://dx.doi.org/10.1145/1952522.1952529

Patel K; Parameswaran S; Ragel RG, 2011, 'Architectural frameworks for security and reliability of MPSoCs', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 19, pp. 1641 - 1654, http://dx.doi.org/10.1109/TVLSI.2010.2053856

Ambrose JA; Ragel RG; Parameswaran S; Ignjatovic A, 2011, 'Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks', IET Computers and Digital Techniques, 5, pp. 1 - 15, http://dx.doi.org/10.1049/iet-cdt.2009.0097

Javaid H; He X; Ignjatovic A; Parameswaran S, 2010, 'Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications', 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010, pp. 75 - 84

Henkel J; Parameswaran S, 2010, 'CASES 2009 guest editor's introduction', Design Automation for Embedded Systems, 14, pp. 285 - 286, http://dx.doi.org/10.1007/s10617-010-9060-4

Javaid H; Ignjatovic A; Parameswaran S, 2010, 'Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29, pp. 1777 - 1789, http://dx.doi.org/10.1109/TCAD.2010.2061353

Chong YJ; Parameswaran S, 2009, 'Custom floating-point unit generation for embedded systems', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650

Chong Y; Parameswaran S, 2009, 'Custom Floating-Point Unit Generation for Embedded Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650

Radhakrishnan S; Guo HA; Parameswaran S; Ignjatovic A, 2009, 'HMP-ASIP`s: heterogeneous multi-pipeline application-specific instruction-set processors', IET Computers and Digital Techniques, 3, pp. 94 - 108

Avnit K; D Silva V; Sowmya A; Ramesh S; Parameswaran S, 2009, 'Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis', ACM Transactions on Design Automation of Electronic Systems, 14

Shee SL; Erdos A; Parameswaran S, 2008, 'Architectural exploration of heterogeneous multiprocessor systems for JPEG', International Journal of Parallel Programming, 36, pp. 140 - 162, http://dx.doi.org/10.1007/s10766-007-0040-7

Parameswaran S; Wolf T, 2008, 'Embedded systems security - an overview', Design Automation for Embedded Systems, 12, pp. 173 - 183

Peddersen JM; Parameswaran S, 2008, 'Energy driven application self-adaptation at run-time', Journal of Computers (JCP), 3, pp. 14 - 24

Wolf T; Parameswaran S, 2008, 'Guest editorial for special issue on embedded system security', Design Automation for Embedded Systems, 12, pp. 171 - 172

Peddersen JM; Parameswaran S, 2008, 'Low-impact processor for dynamic runtime power management', IEEE Design and Test of Computers, 25, pp. 52 - 62, http://dx.doi.org/10.1109/MDT.2008.23

Parameswaran S; Henkel J; Cheung N, 2007, 'Instruction matching and modeling', , pp. 257 - 280, http://dx.doi.org/10.1016/B978-012369526-0/50012-7

Lu IS; Weste N; Parameswaran S, 2007, 'A power-efficient 5.6-GHz process-compensated CMOS frequency divider', IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 54, pp. 323 - 327, http://dx.doi.org/10.1109/TCSII.2006.889741

Peddersen J; Parameswaran S, 2007, 'Low-Impact processor for dynamic runtime power management', IEEE Design & Test of Computers, 24, pp. x4 - x4, http://dx.doi.org/10.1109/mdt.2007.4343581

Janapsatya AG; Ignjatovic A; Parameswaran S, 2006, 'Exploiting statistical information for implementation of instruction scratchpad memory in embedded systems', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 14, pp. 816 - 829

Parameswaran S; Henkel J, 2005, 'Instruction code mapping for performance increase and energy reduction in embedded computer systems', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 13, pp. 498 - 502

Sachdev PS, 2004, 'Foreword', Sensorium - A neuroscience journal for Australasian clinicians, Issue 5, pp. 1 - 1

Janapsatya AG; Henkel J; Parameswaran S, 2004, 'REMcode: relocating embedded code for improving system efficiency', IEE Proceedings-Computers and Digital Techniques, 151, pp. 457 - 465

Rae A; Parameswaran S, 2001, 'Synthesising application-specific heterogeneous multiprocessors using differential evolution', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, pp. 3125 - 3131, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000172877000020&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1

Rae A; Parameswaran S, 2001, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, pp. 2296 - 2302, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000171700800027&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1

Parameswaran S; Henkel J, 2001, 'I-CoPES: Fast instruction code placement for embedded systems to improve performance and energy efficiency', IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers, pp. 635 - 641, http://dx.doi.org/10.1109/ICCAD.2001.968728

Rae A; Parameswaran S, 2001, 'Synthesising application-specific heterogeneous multiprocessors using differential evolution', IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E84-A, pp. 3125 - 3131

Rae A; Parameswaran S, 2001, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E84-A, pp. 2296 - 2302

Parameswaran S; Parkinson MF; Bartlett P, 2000, 'Profiling in the ASP codesign environment', Journal of Systems Architecture, 46, pp. 1263 - 1274, http://dx.doi.org/10.1016/S1383-7621(00)00016-3

Kia SM; Parameswaran S, 1999, 'Self-checking synchronous controller design', IEE Proceedings Computers and Digital Techniques, 146, pp. 9 - 12, http://dx.doi.org/10.1049/ip-cdt:19990243

Parameswaran S, 1998, 'HW-SW co-synthesis: The present and the future', Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 19 - 22

Parameswaran S; Guo H, 1998, 'Power reduction in pipelines', Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 545 - 550

Guo H; Paramewaran S, 1998, 'Unrolling loops with indeterminate loop counts in system level pipelines', Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 99 - 104

Kia SM; Parameswaran S, 1998, 'Designs for self checking flip-flops', IEE Proceedings Computers and Digital Techniques, 145, pp. 81 - 88, http://dx.doi.org/10.1049/ip-cdt:19981907

Jha P; Parameswaran S; Dutt N, 1995, 'Reclocking controllers for minimum execution time', IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E78-A, pp. 1715 - 1721

Jha P; Parameswaran S; Dutt N, 1995, 'Reclocking controllers for minimum execution time', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E78A, pp. 1715 - 1721, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:A1995TM34400016&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1

Conference Papers

Liyanage K; Gamaarachchi H; Saadat H; Li T; Samarakoon H; Parameswaran S, 2024, 'Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions', in Proceedings Design Automation and Test in Europe Date

Bhargavi MB; Siddharth Rokkam S; Parameswaran S; Soumya J, 2024, 'Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA', in 2024 28th International Symposium on VLSI Design and Test Vdat 2024, http://dx.doi.org/10.1109/VDAT63601.2024.10705744

Bhargavi MB; Sai Harshith GS; Parameswaran S; Soumya J, 2024, 'Optimizing LU Decomposition with RISC-V Based Hardware Acceleration', in Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi, pp. 210 - 215, http://dx.doi.org/10.1109/ISVLSI61997.2024.00047

Gong J; Saadat H; Javaid H; Gamaarachchi H; Taubman D; Parameswaran S, 2024, 'SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators', in Proceedings Design Automation and Test in Europe Date

Udugama B; Jayasinghe D; Parameswaran S, 2024, 'Sensors for Remote Power Attacks: New Developments and Challenges', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 333 - 340, http://dx.doi.org/10.1109/ASP-DAC58780.2024.10473890

Jayasinghe D; Udugama B; Parameswaran S, 2023, 'FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers', in Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, pp. 365 - 371, http://dx.doi.org/10.1145/3566097.3568353

Gamaarachchi H; Liyanage K; Parameswaran S, 2023, 'Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis', in Proceedings Design Automation Conference, http://dx.doi.org/10.1109/DAC56929.2023.10247772

Li T; Parameswaran S, 2022, 'FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks', in Proceedings Design Automation Conference, pp. 541 - 546, http://dx.doi.org/10.1145/3489517.3530491

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