ORCID as entered in ROS
https://orcid.org/0000-0003-0380-3506
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Conference Papers
, 2008, 'Exploiting loop-dependent stream reuse for stream processors', in Parallel Architectures and Compilation Techniques Conference Proceedings Pact, pp. 22 - 31, http://dx.doi.org/10.1145/1454115.1454121
, 2008, 'A gather/scatter hardware support for efficient fast fourier transform', in 13th IEEE Asia Pacific Computer Systems Architecture Conference Acsac 2008, http://dx.doi.org/10.1109/APCSAC.2008.4625444
, 2008, 'Thread sensitive module scheduling for multicore processors', in 37th international conference on parallel processing, Portland, Oregon, USA, presented at
, 2008, 'A gather/scatter hardware support for efficient fast Fourier transform', in ACSAC 2008 13th IEEE Asia-Pacific computer systems architecture conference, Hsinchu, Taiwan, pp. 1 - 8, presented at
, 2008, 'Optimizing scientific application loops on stream processors', in ACM SIGPLAN Notices, pp. 161 - 170, http://dx.doi.org/10.1145/1379023.1375679
, 2008, 'Optimizing scientific application loops on stream processors', in ACM Sigplan Notices, Association of Computing Machinery, New York, NY, USA, presented at
, 2007, 'Loop recreation for thread-level speculation', in 13th International Conference on Parallel and Distributed Systems (ICPADS 2007), Hsinchu, Taiwan, presented at
, 2007, 'Toward automatic data distribution for migrating computations', in 2007 International conference on parallel processing, China, presented at
, 2007, 'Towards data tiling for whole programs in scratchpad memory allocation', in 12th Asia-Pacific computer systems architecture conference, Korea, presented at
, 2007, 'Validity invariants and effects', in 21st European conference on object oriented programming, Berlin, Germany, presented at
, 2007, 'Scratchpad allocation for data aggregates in superperfect graphs', in 2007 ACM conference on languages, compilers and tools for embedded systems, San Diego, Californa, USA, presented at
, 2006, 'Minimizing Bank Selection Instructions for Partitioned Memory Architectures', in International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Seoul, South Korea, presented at
, 2006, 'Trace-based cache leakage reduction at link time', in Advances in computer systems architecture, 11th Asia-Pacific conference, Shanghai, China, presented at
, 2006, 'Instruction scheduling with release times and deadlines on ILP processors', in 12th IEEE international conference on embedded and real-time computing systems, Sydney, presented at
, 2006, 'CoopStream: a cooperative cache based streaming schedule scheme for on-demand media services on overlay networks', in International conference on parallel processing, Columbus, Ohio, USA, presented at
, 2006, 'Message from IWEC workshop co-chairs', in Proceedings of the International Conference on Parallel Processing Workshops, pp. xvii - xviii, http://dx.doi.org/10.1109/ICPPW.2006.47
, 2006, 'A fresh look at PRE as a maximum flow problem', in 15th international conference on compiler construction, Vienna, Austria, presented at
, 2006, 'Instruction Scheduling with Release Times and Deadlines on ILP Processors', in Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, IEEE, Sydney, presented at
, 2005, 'Compiler-directed scratchpad memory management', in Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, pp. 2, http://dx.doi.org/10.1007/11599555_2
, 2005, 'Fast parallel DNA-based algorithms for molecular computation: Determining a prime number', in Proceedings 3rd International Conference on Information Technology and Applications Icita 2005, pp. 447 - 452
, 2005, 'Aggressive loop fusion for improving locality and parallelism', in Proceedings of the First International Conference on Advances in Natural Computation (ICNC 2005), Part III, Lecture Notes in Computer Science 3612/2005, Springer, Berlin, Germany, presented at
, 2005, 'Improving the performance of GCC by exploiting IA-64 architectural features', in Proceedings of the First International Conference on Advances in Natural Computation (ICNC 2005), Part III, Lecture Notes in Computer Science 3612/2005, Springer, Berlin, Germany, presented at
, 2005, 'Memory coloring: a compiler approach for scratchpad memory management', in 1th International conference on parallel architectures and compilation, Saint Louis, Missouri, USA, presented at
, 2005, 'Enabling loop fusion and tiling for cache performance by fixing fusion-preventing data dependencies', in 2005 international conference on parallel processing, Oslo, Norway, presented at
, 2005, 'Completeness analysis for incomplete object-oriented programs', in 2005 international conference on compiler construction, Edinburgh, Scotland, presented at
, 2005, 'Interprocedural side-effect analysis and optimisation in the presence of dynamic class loading', in 28th Australasian computer science conference ACSC 2005, Newcastle, NSW, presented at
, 2004, 'A trace-based binary compilation framework for energy-aware computing', in Language, Compilers, and Tools for Embedded Systems, Washington DC, USA, presented at
, 2004, 'A Comparative Study of Web Application Design Models Using the Java Technologies', in 6th Asia-Pacific Web Conference 2004, Hangzhou, China, presented at
, 2004, 'Region-Based Partial Dead Code Elimination on Predicated Code', in 13th International Conference on Compiler Construction, Barcelona, Spain, presented at
, 2004, 'Strength Reduction for Loop-Invariant Types', in 27th Australasian Computer Science Conference, Dunedin, New Zealand, presented at
, 2004, 'A trace-based binary compilation framework for energy-aware computing', in Proceedings of the ACM SIGPLAN Conference on Languages Compilers and Tools for Embedded Systems LCTES, pp. 95 - 106, http://dx.doi.org/10.1145/997163.997178
, 2003, 'Data caches in mutitasking hard real-time systems', in 24th IEEE International Real-Time Systems Symposium, Cancun, Mexico, presented at
, 2003, 'Code Tiling For Improving the Cache Performance of PDE Solvers', in 2003 International Conference on Parallel Processing, Taiwan, presented at
, 2003, 'Data cache locking for higher program predictability', in 2003 Joint International Conference on Measurement and Modeling of Computer Systems, San Diego, Californa, USA, presented at
, 2003, 'Data cache locking for higher program predictability', in Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, ACM, pp. 272 - 282, presented at
, 2003, 'Optimal and Efficient Speculation-Based Partial Redundancy Elimination', in International Symposium on Code Generation and Optimization (CGO 2003), San Francisco, California USA, presented at
, 2002, 'Efficient Compile-Time Analysis of Cache Behaviour for Programs with IF Statements', in 5th International Conference on Algorithms and Architectures for Parallel Processing, Beijing, China, presented at
, 2002, 'A generic localization method for VLSI implementation of algorithms.', in 4th International Conference on Massively Parallel Computng Systems, Ischia, pp. 396 - 407, presented at
, 2002, 'Let`s Study Whole-Program Cache Behaviour Analytically', in 8th International Symposium on High-Performance Computer Architecture, Cambridge, Massachusetts, USA, presented at
, 2001, 'On Nonsingular Loop Transformations Using SUIF`s Dependence Abstraction', in 2nd international conference on parallel and distributed computing, applications and technologies, TAIWAN, presented at
, 2000, 'Time-Minimal and Processor-Time-Minimal Loop Tiling', in 4th International Conference on Algorithms and Architectures for Parallel Processing, Hong Kong, presented at
, 2000, 'Optimal tiling for loops with parallelogram iteration spaces', in 1st International Conference on Parallel and Distributed Applications and Technologies, Hong Kong, presented at
, 1999, 'Communication Overhead on Distributed Memory Machines', in 4th Australasian Computer Architecture Conference, Auckland, New Zealand, presented at
, 1998, 'Issues of tiling double loops on distributed memory machines', in he 5th Australasian Conference on Parallel and real-time systems, Springer, Adelaide, pp. 377 - 388, presented at
, 1998, 'An expert control system for gas furnace pressure', in proceedings of the Second IEEE International Conference on Intelligent Processing, Gold Coast : Griffith University, 1998, Gold Coast, presented at
, 1997, 'Eigenvectors-based parallelisation of nested loops with affine dependences', in Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97., 1997 3rd International Conference on, IEEE, Melbourne, pp. 357 - 366, presented at
, 1997, 'Reuse-driven tiling for data locality', in Lecture Notes in Computer Science, Springer, Minnesota, pp. 16 - 33, presented at
, 1996, 'Communication-minimal tiling of uniform dependence loops', in Lecture Notes in Computer Science, Springer, San Jose, pp. 330 - 349, presented at
, 1996, 'On loop restructuring by converting imperfect to perfect loop nests', in IEEE 2nd International Conference on Algorithms and Architectures for Parallel Processing, IEEE, Singapore, pp. 421 - 429, presented at
, 1996, 'Affine-by-Statement Transformations of Imperfectly Nested Loops', in Proceedings of the 10th International Parallel Processing Symposium, Hawaii, presented at
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https://orcid.org/0000-0003-0380-3506