ORCID as entered in ROS
https://orcid.org/0000-0003-0881-1548
Select Publications
Conference Papers
, 2005, 'Feasibility of Air Target Detection Using GPS as a Bistatic Radar', in Proceedings of GNSS 2005, Hong Kong, presented at
, 2005, 'FPGA based GPS receiver design considerations', in Proceedings of GNSS 2005, Scientific Research Publishing Inc, Hong Kong, presented at
, 2005, 'Probabilistic Algorithm to Support the Fingerprinting Method for CDMA Location', in Proceedings of GNSS 2005, Hong Kong, presented at
, 2005, 'Indoor GPS positioning', in VTC2005-FALL: 2005 IEEE 62ND VEHICULAR TECHNOLOGY CONFERENCE, 1-4, PROCEEDINGS, IEEE, TX, Dallas, pp. 412 - 415, presented at
, 2005, 'Application of Interpolation to Mobile Phone Fingerprinting for Positioning', in Proceedings of ION-GNSS 2005, Long Beach, CA, presented at
, 2005, 'A Novel GPS Cross Correlation Mitigation Technique', in Proceedings of the 18th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2005), The Institute of Navigation (ION), Long Beach, CA, pp. 190 - 199, presented at
, 2005, 'CHARACTERIZATION OF INTERFERENCE EFFECTS ON GPS SIGNAL CARRIER PHASE ERROR', in national biennial Conference of the spatial Sciences Institute, Spatial Science Institute, Melbourne, presented at
, 2005, 'Hybrid Method for Localization Using WLAN', in national biennial Conference of the spatial Sciences Institute, Spatial Science Institute, Melbourne, presented at
, 2005, 'Trade-offs in low-power multiplier blocks using serial arithmetic', in Proceedings of Nat Conf Radio Sci, Linkoping, Sweden, presented at
, 2005, 'Synthesis of Reconfigurable Multiplier blocks: Part I - Fundamentals', in Circuits and Systems, 2005, Kobe, Japan, presented at
, 2005, 'Multiplication by two integers using the minimum number of adders', in IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, presented at
, 2005, 'Synthesis of Reconfigurable Multiplier Blocks: Part II - Algorithm', in IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, presented at
, 2005, 'Blood Cell Segmentation Using Minimum Area Watershed and Circle Radon Transformations', in Proceedings of the International Symposium on Mathematical Morphology, Kluwer Academic Publishers, the Netherlands, presented at
, 2005, 'Indoor GPS positioning - Challenges and opportunities', in IEEE Vehicular Technology Conference, pp. 412 - 415, http://dx.doi.org/10.1109/VETECF.2005.1557943
, 2004, 'New GNSS Signals: Receiver Design Challenges', in Positioning, Scientific Research Publishing, Inc., United States, presented at
, 2004, 'Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic', in Proceedings of the Mediterranean Electrotechnical Conference MELECON, pp. 197 - 200
, 2004, 'Comparison of Graphical and Sub-expression Elimination Methods for Design of Efficient Multipliers', in Proceedings of Asilomar Conference on Signals, Systems, and Computers, Monterey, presented at
, 2004, 'Efficient Implementation of Digital Filters using Noevel Reconfigurable Multiplier Blocks (ReMB)', in Proceedings of Asilomar Conference on Signals, Systems, and Computers, Monterey, presented at
, 2004, 'Low complexity hybrid form FIR filters using matrix multiple constant multiplication', in Proceedings of Asilomar Conference on Signals, Systems, and Computers, Monterey, presented at
, 2004, 'On the use of multiple constant multiplication in polyphase FIR filters and filter banks', in Proceedings of NORSIG 2004, Reykjavik, Iceland, presented at
, 2004, 'Digital Filter Design Using Subexpression Elimination And All Signed-Digit Representations', in Proceedings of ISCAS 2004, Vancouver, presented at
, 2004, 'Multiplier Blocks Using Carry-Save Adders', in Proceedings of ISCAS 2004, Vancouver, presented at
, 2004, 'Using All Signed-Digit Representations To Design Single Integer Multipliers Using Subexpression Elimination', in Proceedings of ISCAS 2004, Vancouver, presented at
, 2004, 'Multiplier blocks using carry-save adders', in 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, IEEE, CANADA, Vancouver, pp. 473 - 476, presented at
, 2004, 'A Review of GPS Cross Correlation Mitigation Techniques', in Positioning, Scientific Research Publishing, Inc., United States, presented at
, 2003, 'Towards an Algorithm for Matrix Multiplier Blocks', in Proceedings of European Conference on Circuit Theory and Design, Krakow, Poland, presented at
, 2003, 'Desingn guidelines for reconfigurable multiplier blocks', in PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, IEEE, THAILAND, BANGKOK, pp. 293 - 296, presented at
, 2003, 'Reconfigurable implementation of recursive DCT kernels for reduced quantization noise', in PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, IEEE, THAILAND, BANGKOK, pp. 289 - 292, presented at
, 2003, 'Design Guidelines for Reconfigurable Multiplier Blocks', in Proceedings of ISCAS 2003, Bangkok, presented at
, 2003, 'Reconfigurable Implementation of Recursive DCT Kernels for Reduced Quantization Noise', in Proceedings of the ISCAS 2003, Bangkok, presented at
, 2002, 'Power consumption behaviour of multiplier block algorithms', in Midwest Symposium on Circuits and Systems, pp. III1 - III4
, 2002, 'Designing multiplier blocks with low logic depth', in 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, IEEE, AZ, PHOENIX, pp. 773 - 776, presented at
, 2002, 'Power analysis of multiplier blocks', in 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS, IEEE, AZ, PHOENIX, pp. 297 - 300, presented at
, 2002, 'Designing multiplier blocks with low logic depth', in Proceedings IEEE International Symposium on Circuits and Systems, pp. V/776
, 2002, 'Extended results for minimum-adder constant integer multipliers', in Proceedings IEEE International Symposium on Circuits and Systems, pp. 73 - 76, http://dx.doi.org/10.1109/ISCAS.2002.1009780
, 2002, 'Modification on distance transform to avoid over-segmentation and under-segmentation', in Proceedings Vipromcom 2002 4th Eurasip IEEE Region 8 International Symposium on Video Image Processing and Multimedia Communications, pp. 295 - 301, http://dx.doi.org/10.1109/VIPROM.2002.1026672
, 2002, 'Power analysis of multiplier blocks', in Proceedings IEEE International Symposium on Circuits and Systems, pp. I/300
, 2002, 'Use of area-closing to improve granulometry performance', in Proceedings Vipromcom 2002 4th Eurasip IEEE Region 8 International Symposium on Video Image Processing and Multimedia Communications, pp. 303 - 308, http://dx.doi.org/10.1109/VIPROM.2002.1026673
, 2001, 'Using carry-save adders in low-power multiplier blocks', in Iscas 2001 2001 IEEE International Symposium on Circuits and Systems Conference Proceedings, pp. 222 - 225, http://dx.doi.org/10.1109/ISCAS.2001.922212
, 2001, 'Transition reduction in multiplier-block based digital filters', in IEE Colloquium Digest, pp. 87 - 92
, 2001, 'Morphological image processing for evaluating malaria disease', in Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, pp. 739 - 748, http://dx.doi.org/10.1007/3-540-45129-3_68
, 2001, 'Novel recursive-DCT implementations: A comparative study', in Proceedings of the International Workshop on Intelligent Data Acquisition and Advanced Computing Systems Technology and Applications Idaacs 2001, pp. 120 - 123, http://dx.doi.org/10.1109/IDAACS.2001.941994
, 2001, 'Using carry-save adders in low-power multiplier blocks', in Materials Research Society Symposium Proceedings, pp. IV222 - IV225
, 2001, 'Using granulometries in processing images of malarial blood', in Iscas 2001 2001 IEEE International Symposium on Circuits and Systems Conference Proceedings, pp. 291 - 294, http://dx.doi.org/10.1109/iscas.2001.922042
, 2000, 'Transition analysis on FPGA for multiplier-block based FIR filter structures', in Proceedings of the IEEE International Conference on Electronics Circuits and Systems, pp. 862 - 865, http://dx.doi.org/10.1109/ICECS.2000.913012
, 1997, 'Cost of limit-cycle elimination in IIR digital filters using multiplier blocks', in Proceedings IEEE International Symposium on Circuits and Systems, pp. 2204 - 2207
, 1996, 'Reducing complexity by increasing order of IIR digital filters', in Proceedings of the IEEE International Conference on Electronics Circuits and Systems, pp. 522 - 525
, 1995, 'Variation of FIR filter complexity with order', in Midwest Symposium on Circuits and Systems, pp. 342 - 345
, 1995, 'Comparison of IIR filter structure complexities using multiplier blocks', in Proceedings IEEE International Symposium on Circuits and Systems, pp. 858 - 861
, 1994, 'Use of multiplier blocks to reduce filter complexity', in Proceedings IEEE International Symposium on Circuits and Systems, pp. 263 - 266
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https://orcid.org/0000-0003-0881-1548